About The Product

EdvFormal helps semiconductor teams verify RTL designs using formal methods, SystemVerilog Assertions, connectivity specifications, equivalence checks, and AI-assisted verification workflows.

It reduces manual verification effort, improves bug detection, and helps engineers find design issues earlier than simulation-only approaches.

Key Features

FCC – Formal Connectivity Check

Verifies whether specified digital connections, paths, mux selections, and register paths are correctly implemented in RTL.

FPV – Formal Property Verification

Verifies RTL behavior against SVA properties. Useful for proving protocol rules, design intent, and corner-case behavior.

FEC – Formal Equivalence Check

Compares two design versions to prove functional equivalence after RTL changes, optimization, or transformation.

FTA – Formal Testbench Analyzer

Analyzes the quality and effectiveness of SVA testbenches using formal/mutation-based techniques.

Multiple Engine Support

Supports multiple formal engines/solvers to improve flexibility across different designs.

Multiple Verification Modes

Supports BMC and Prove modes for bug hunting and bounded proof.

AI-Assisted Formal Verification

Uses AI agents to assist with assertion generation, debug guidance, and future proof-convergence support.

How It Works?

Provide Design Inputs
User provides RTL files and required configuration.
Select Application Mode
The user selects FPV, FCC, FEC, or FTA based on the verification task.
Provide Verification Intent
For FPV, provide SVA. For FCC, provide connectivity specification. For FEC, provide reference and revised RTL. For FTA, provide SVA testbench-related inputs.
AI Assistance
AI agent helps generate assertions, interpret requirements, assist debug, and guide verification closure.
Configure Run
The user selects mode, solver/engine, depth, clock/reset, and other options.
Run Formal Analysis
EdvFormal executes the formal verification flow using selected engines.
Review Results
Tool reports pass/fail results depending on mode.
Debug and Iterate
Engineers use logs, reports, and VCD traces to fix RTL/properties/specs and rerun verification.

Who Is It For?

Design Verification Engineers
Formal Verification Engineers
ASIC and FPGA teams

Frequently Asked Questions

Why choose EDVFormal?
  • Combines formal verification with AI-assisted engineering support.
  • Supports multiple formal application modes: FPV, FCC, FEC, and FTA.
  • Reduces manual effort in assertion writing, connectivity checking, equivalence checking, and debug.
  • Helps catch deep corner-case bugs earlier than simulation-only verification.
What does the product produce or deliver?
  • FPV pass/fail/cover results
  • FCC connectivity check results
  • FEC equivalence/non-equivalence results
  • FTA testbench analysis results
  • Formal logs and reports
  • VCD waveform traces for debug
  • AI-assisted assertion/debug recommendations
What information or files does the product need to get started?
  • 1. TCL file containing below information
  • RTL files
  • SystemVerilog Assertions for FPV
  • Connectivity specification for FCC
  • Reference and revised RTL for FEC
  • Testbench/design inputs for FTA
  • Top module details
  • Clock and reset information

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