About The Product
Feed EDVA the chip specification and it generates RTL, testbenches, assertions(SVA), register models(RAL), verification plans, and coverage code then runs simulation, analyses the results, and automatically resolves any issues found.
When engineers need to go deeper, the AI Chat Assistant runs simulations, controls the waveform viewer, writes files, and generates verification artifacts all through natural conversation.
Runs Natively on your infrastructure. Integrates with Questa, Cadence, Synopsys, or Icarus Verilog. Accessible via GUI or CLI.
Key Features
Hybrid RAG Specification Engine
EDVA processes and indexes your entire chip specification using a hybrid retrieval-augmented generation engine combining dense vector search with keyword-based retrieval to ensure the most relevant specification context is always used during generation. Every RTL module, testbench, assertion, and verification artifact is grounded in precise, retrieved specification data.
Verification Plan
Four Parts, interactive EDVA builds a complete, structured verification plan with engineer review at every stage: Features and Functionalities — every chip feature extracted, prioritized, and traced to the spec. Test Plan — full test scenarios per feature across all test types. Checker Plan — Signal Level Assertion (SLA) and data-level checker requirements, categorized. Coverage Plan — Cover groups, Cover points, Bins and Cross coverage precisely defined.
Coverage Code Generation
EDVA converts the approved coverage plan into working coverage implementation files ready to drop into any testbench. No manual translation required.
RTL coder
EDVA reads your chip specification and generates RTL from signal definitions and module hierarchy to fully implemented logic. Every stage is lint-verified. Every ambiguity is flagged before a single line of code is written.
Testbench Coder
EDVA generates self-checking testbench covering reset behavior, normal operation, boundary and corner cases, state transitions, protocol edge-cases, error conditions, and every mode defined in the spec. Expected outputs are computed from a reference model derived from the specification - not guesswork - enabling automated pass/fail checking via scoreboards and assertions.
FSM Diagrams
EDVA extracts the FSM details from the spec including those inside embedded images and renders clean, accurate state diagrams automatically.
Waveform Viewer
EDVA includes a waveform viewer with signal browser, hierarchy navigation, zoom, and signal freeze. VCD compare, config (.rc) file load/save, signal tracer, schematic tracer and marker-based timing analysis controlled directly from the Chat Assistant.
AI Chat Assistant
EDVA's Chat Assistant is your AI engineering partner with full access to the indexed specification through the hybrid RAG engine. Ask it to debug a simulation failure, query the spec, trace a signal, open a waveform, write a file, run a simulation, or generate an artifact all through natural conversation. Debug RTL failures using combined code, spec, and simulation log context. Analyze waveforms: open VCD files, display signals, mark regions, add bookmarks from chat. Query any specification detail with precise, source-cited answers instantly. Write and edit any file with precise edits, multi-file patches, full edit history. Run simulations, parse results, iterate from conversation. Generate any artifact: assertions, register models, coverage code, FSM diagrams, verification plans.
On-Premises
EDVA runs natively on your infrastructure. No specification, RTL, or design data ever leaves your environment. Built for an industry where IP confidentiality is non-negotiable. GUI and CLI based application for interactive use, and a command-line interface for automation and pipeline integration — every capability, both ways.
How EDVA Works?
Process and index chip specifications using a hybrid RAG engine for precise, context-aware generation.
Generate RTL design from chip specification automatically.
Build a four-part verification plan — interactively, with engineer review.
Produce a full testbench from register specification and register-level files.
Generate a complete assertion suite from the design and specification.
Generate coverage implementation code from the approved coverage plan.
Render FSM diagrams for every state machine in the spec.
Generate self-checking testbenches covering every scenario in the spec.
Run simulations and debug failures automatically until the design passes.
Who Is It For?
RTL Design Engineers
Design Verification Engineers
Frequently Asked Questions
Why choose Edva?
- Specification-Grounded Generation. EDVA's hybrid RAG engine indexes your entire specification — text, tables, and images — and retrieves the precise context needed for every generation task. Every output traces back to your spec.
- One Tool. Design and Verification Both. RTL, testbenches, simulation, assertions, register models, verification plans, coverage — all from one spec, one tool.
- Reads Images Too. Block diagrams, FSM diagrams, timing diagrams inside your spec. EDVA reads them all.
- EDVA's Chat Assistant debugs RTL, runs simulations, controls waveform viewers, writes and updates the code. Not a chatbot. An AI engineer.
- EDVA fixes simulation failures automatically and only moves forward when everything passes.
- Your IP Stays on Your Machines. Full AI capability. Zero cloud dependency. Complete data control.
What information or files does the product need to get started?
| Input | Format |
|---|---|
| Chip Specification Documents | PDF, DOCX |
| Register Specification Documents (optional) | PDF, DOCX |
| Register Definition Files (optional) | Excel |
| RTL and Testbench Files (optional) | Verilog, SystemVerilog |
What does the product produce or deliver?
- RTL Design Files — Synthesizable chip design modules
- Testbench Files — Self-checking testbenches with full scenario coverage
- Assertion Suite — Complete assertions for all chip behaviours
- Register Model Package — Fields, hierarchy, and coverage — testbench-compatible
- FSM Diagrams — Visual state machine diagrams from the spec
- Verification Plan — Features, Test Plan, Checker Plan, Coverage Plan
- Coverage Code — Ready-to-use coverage implementation files
- Simulation Results — Logs, VCD waveforms, error analysis
